The present invention relates to an IC (Integrated Circuit) and more particularly to a clock distribution system for distributing a multiphase clock to the internal circuitry of an IC.
Today, a clock frequency required of a LSI (Large Scale Integrated circuit) is entering a gigahertz band and must be implemented by a multiphase clock. In this respect, it is necessary to reduce not only a clock skew in each phase but also a clock skew between different phases. To feed clocks of different frequencies to the internal logical circuit of a LSI, a plurality of different clock distribution paths are indispensable. As for a clock skew between different phases, assume that a multiphase clock has a frequency produced by dividing the frequency of a reference clock or normal clock by an integer. Then, a clock skew between different phases refers to a skew between the positive-going or the negative going of the divided clock (1/n) and the reference clock from which the above edge is produced.
Assume that a plurality of clock distribution paths sharing a single clock input point are laid on a LSI by extending a conventional scheme. Then, as for a clock skew between different phases, a clock distribution delay and the influence of scatter in production and noise increase. While design margins may be increased in order to stabilize the operation of the LSI, increased margins limit the performance of the LSI. Particularly, when clocks lying in the gigahertz band are distributed to a LSI, fine buffering is essential in order to cope with the skin effect of wirings, reflection and other physical characteristics, tending to aggravate the clock distribution delay. This is one of major causes that obstruct skew reduction. Further, scatter in the production of LSIs, which has not been discussed in the past, is a problem in further scaling up LSIs.
The easiness of design is a prerequisite for reducing a TAT (Turn-Around Time) in the development of LSIs. To reduce a TAT, Japanese Patent Laid-Open Publication No. 8-55962, for example, discloses a system in which a clock source (buffer) and its output are wired in order to allow delays to be matched (skew reduction) at the design stage and to reduce the influence of scatter in production. Japanese Patent Application No. 10-205361 teaches a configuration in which a clock distribution system using clock wirings easily reduces a clock skew.
However, none of the prior art schemes even suggests a measure against skew reduction in relation to the distribution of a multiphase clock. Therefore, there is an increasing demand for multiphase clock distribution realizing skew reduction without resorting to any noticeable modification of the conventional clock distribution arrangement.
Technologies relating to the present invention are also disclosed in, e.g., Japanese Patent Laid-Open Publication Nos. 5-159080, 8-190443, 9-130370, and 11-328244.
It is therefore an object of the present invention to provide an IC capable of reducing a clock skew when a multiphase clock is distributed to its internal circuitry.
In accordance with the present invention, an IC including internal circuitry to which a multiphase clock is distributed includes 1/n clock, main wiring drivers each including a frequency divider for dividing the frequency of an input clock by n and a drive circuit for delivering the resulting 1/n clock to a corresponding 1/n clock main wiring. Normal clock, main wiring drivers each include a delay for delaying an input clock to thereby output a normal clock and a drive circuit for delivering the normal clock to a corresponding normal clock main wiring. A clock distributing circuit includes clock wirings for distributing a clock input via a clock input circuit and a plurality of repeat buffers for distributing the distributed clock to each of the 1/n clock and normal clock, main wiring drivers. The IC additionally includes a wiring wiring the outputs of the repeat buffers, a wiring wiring the outputs of 1/n clock, main wiring drivers, and wiring wiring the outputs of the normal clock, main wiring drivers.